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PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 177
16.7
A/D Conversions
Figure 16-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 16-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT2:ACQT0
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion
sample.
This
means
that
the
ADRESH:ADRESL registers will continue to contain the
value of the last completed conversion (or the last value
written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2TAD wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
16.8
Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
FIGURE 16-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 16-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY – TAD
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle:
TAD1
Discharge
1
2
3
4
5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
TACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
TAD1
Discharge
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